| interfaces: -LVCMOS 3.3/2.5/1.671.5/1.2 - LVTTL - SSTL 18 Class 1 - SSTL 3/2 Class I, II -HSTL15 Class I, 111 - HSTL 18 Class 1,11, III - PCI - LVDS. Bus-LVDS, LVPECL, RSDS Dedicalcd DDR Memory Support • implements interfaces up to DDR333 (166MHz) SysCLOCK™ PLLs • I p In 4 analog i*l I - fir I device • 1. lock multiply, divide and phase shifting Sleep Mode Reduces Siandhy Power to <10(ipA Sysiem I eve I Siijipoil ■ IEEE Standard 1149.1 Boundary Scan, plus ispTRACV™ internal logic analyzer capability • Onboard oscillator for configuration • Operate with 3.3V, 2.5V, 1.8V or 1.2V power supply |