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LOW-COST FPGAs WITH HIGH PERFORMANCE DSPs

I0169 E-LatticeECP/EC Families Product Brief - 30624 LatticeECP & EC Families

Exceptional Performance with Uncommon Value

Since 1985, Lattice has led the programmable logic industry by bringing the best together to provide design engineers with the most innovative programmable products. Now, Lattice brings you a new generation of optimized low- cost FPGAs. For maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated func- tions. Lattice’s first family to implement this approach is the LatticeECP-DSP (EConomy Plus DSP) family, provid- ing dedicated high-performance DSP blocks on-chip. The LatticeEC™ (EConomy) family supports all the general-pur- pose features of LatticeECP devices without dedicated func- tion blocks to achieve even lower cost solutions.The LatticeECP and EC families both utilize a silicon-efficient FPGA fabric in which I/O capability, distributed memory, embedded memory, logic and routing have been optimized to provide the best features at value-conscious prices.The LatticeECP-DSP devices are ideal for use in applications in which cost-effective DSP functionality is needed. Such applications include software defined radio, wireless com- munications, military applications and video processing equipment. LatticeEC devices are ideal for general non-DSP applications such as low-cost networking, blade servers, network access equipment, consumer electronics, industrial, medical and automotive applications.

Key Features and Benefits

N Low-Cost FPGAs • Features optimized for mainstream applications • Balanced logic / memory / I/O resources
N High Performance sysDSP™ Blocks (LatticeECP-DSP) • Multiply, accumulate, addition and subtraction • Input, intermediate and output pipeline registers • 4 to 8 sysDSP blocks per device – Each block supports multiple 9x9, 18x18, 36x36 multipliers
N Extensive Density and Package Options • 1.5K to 32.8K LUT4s; 67 to 496 I/Os • Density migration supported • TQFP, PQFP and fpBGA packaging options • Pb-free / RoHS compliant options

Superior DSP Performance and Utilization The Most Affordable FPGA Solution

DSP Performance Efficient LUT Utilization (Frequency in MHz) (# of Slices Occupied) 160 1400 N Embedded and Distributed Memory • 18 Kbits to 498 Kbits sysMEM™ Embedded Block RAM (EBR) • Up to 131 Kbits distributed RAM
120 1050 FPGAwithSimpleMultiply 80 ECP withDSP FPGAwithSimpleMultiply 700 N Flexible I/O Buffer • Hot Socketing • Programmable sysIO™ buffer supports wide range of interfaces: – LVCMOS 3.3/2.5/1.8/1.5/1.2 – LVTTL – SSTL 3/2 Class I, II, SSTL18 Class I – HSTL 18 Class I, II, III, HSTL15 Class I, III – PCI – LVDS, Bus-LVDS, LVPECL, RSDS
40 350 ECP withDSP FIR IIR FIR IIR (64-tap,18-bit data) (4th order,18-bit data) (64-tap,18-bit data) (4th order,18-bit data) Relative Cost – LatticeEC vs. Competition 100% 30% to 50%Savings N Dedicated DDR Memory Support
75% FPGABoot PROM • Implements interface up to DDR400 (200MHz)
N sysCLOCK™ PLLs
50% • Up to 4 analog PLLs per device • Clock multiply, divide and phase shifting
LatticeECFPGASPI Flash 25% N System Level Support • Standard IEEE 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability• Industry standard, third-party SPI boot flash interface • 1.2V power supply
LatticeECEC6 Competition Note: Based on competition's low volume, published pricing as of June 1, 2004.

LATTICE: BRINGING THE BEST TOGETHER