I0168E ispClock Product Brief - Lattice Semiconductor - #1

i CK DEVICES

ispClock

Imagine designing your clock nets without using an as­sortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts! The answer is Lattice's revolutionary ispClock5600A family for complex clock nets and ispClock5300S family for simple clock nets. Lattice's ispClock devices can be programmed in­system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements - all while meeting stringent skew and jitter standards!

The ispClock architecture is built around a high perfor­mance PLL with programmable input, feedback, and output circuitry providing the flexibility to generate up to five dif­ferent clock frequencies and route them to any of the output pins. The reference input, feedback input and all outputs can be programmed independently to interface with differ­ent I/O standards. Each output's skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices.

In ispClock5600A devices there are four configuration pro­files stored on-chip for dynamically altering output frequen­cies for power savings, test mlodss and^theupurposesA

The ispClock5300S supports implementation of zero delay and non-zero delay fanout buffers in a single device.

References ^pr°^g," Inputs^ ^Cloc» H I Input

Mdiv-».

Clock Outputs

Profile Management Logic

Feedback

Reference ^Prog" Inputs^ ^Clock

Input

Output Routing Matrix

Clock

Outputs

Fanout Buffer Path

Feedback Input

• A single ispClock device replaces multiple types of clock devices

• Eliminates need for serpentine traces and termination resistors

■ Improved Clock Net Performance | 1» llow jUteJ alndl skem.

• Improved signal integrity

—T ispClockdevites redmcj tihjing unfcep-aimy

• Windows / PC based design

•JTAG programming and Boundary Scan

Integrates Clock Generation and Distribution ICs

✓ Clock Generation

✓ Differential Clock Drivers

✓ Single-Ended Clock Drivers

✓ Zero Delay Buffers

✓ Termination

Integrates Single-Ended Clock Distribution ICs

Device #6

✓ Clock Drivers

✓ Zero Delay Buffers

✓ Fanout Buffers

✓ Termination

Device #n