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| | | Design Made Simple with PAC-Designer Software Lattice's PAC-Designer® software, a PC-based software tool, and Frequency Synthesizer enable easy configuration of provides simple and intuitive pull-down menus for config- various counters and other options. Configurations can be uring all programmable features of the device. In addition, downloaded into ispClock devices from a PC parallel port. design utilities like the Skew Editor, Frequency Calculator r | | |
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| | | . Download design configuration to ispClock5600A for verification. | | 1. Specify I/O interface type. | | |
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| | | 3. Graphically adjust skew for each clock output. | | 2. Synthesize M, N & V counters from output frequencies. | | |
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| | | ispClock Attributes | | |
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| | | | | | | | | | | | | | | ispClock5600A Family | ispClock5300S Family | | | | 5610A | 5620A | 5304S | 5308S | 5312S | 5316S | 5320S | | | | | | | | | | | | | | |
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| | | Outputs | | 12 | | 16 | | 20 | | |
| | | 10 | | 20 | | 4 | | 8 | | |
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| | | Input & Output Frequency Range | | 8 to 400MHz | | 8 to 267MHz (input), 5 to 267MHz (output) | | |
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| | | VCO Operation | | 320 to 800MHz | | 160 to 400MHz | | |
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| | | Spread Spectrum Compatibility | | Yes | | Yes | | |
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| | | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL | | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL | | |
| | | Programmable Input Types | | |
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| | | Programmable Output and Feedback Interface Types | | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL | | |
| | | LVTTL, LVCMOS, SSTL, HSTL | | |
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| | | Type of PLL Feedback | | |
| | | Internal/External | | External | | |
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| | | Maximum Cycle-Cycle Jitter | | |
| | | 70ps (peak-peak) | | 70ps (peak-peak) | | |
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| | | Maximum Period Jitter (RMS) | | |
| | | 12ps | | 12ps | | |
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| | | Maximum Phase Jitter (RMS) | | |
| | | 50ps | | 50ps | | |
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| | | Maximum Static Phase Offset | | |
| | | -100ps to 200ps | | -40ps to 100ps | | |
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| | | Frequencies Generated | | |
| | | 5 | | 3 | | |
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| | | Programmable Skew | | |
| | | 156ps to 12ns | | 156ps to 5ns | | |
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| | | Programmable Termination | | 40 to 70Q & 20Q Setting | | 40 to 70Q & 20Q Setting | | |
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| | | Applications Support 1-800-LATTICE (528-8423) (503) 268-8001 techsupport@latticesemi.com www.latticesemi.com | | |
| | | Semiconductor ■ ■ Corporation More of the Best | | |
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| | | Copyright © 2007 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., Lattice (design), ispClock, ispPAC, PAC-Designer and ispDOWNLOAD are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. | | December 2007 Order #: I0168E | | |
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