16 Power Management and Sleep Modes
16.1 Power Domains
There are six power domains present in the device allowing different parts to be turned off to save power under different operating conditions. These domains are as follows:
•
The VDD supply power domain is directly powered from VDD1, VDD2 that supplies the wake-up timers and
controller, DIO blocks, comparator, 32kHz RC oscillator and bandgap reference. This domain remains powered as long as the external supply is maintained
•
The Application Logic domain comprising the SPI interface, CPU, and ROM is powered from an on-chip regulator. It is powered off during sleep and powered on at wakeup
•
The Analogue Peripheral domain comprising the ADC, DACs and the temperature sensor is powered from an on-chip regulator. It is powered off during sleep and optionally powered on under software control
•
Memory (RAM) power domain provides the ability to power the CPU RAM during sleep periods in order to keep the memory contents. It is powered from an on-chip regulator that is on when the JN5121 is not in sleep and optionally, under software control powered off during sleep
•
The Transceiver Logic domain, comprising the Baseband Controller, Modem and Encryption coprocessor, is powered from an on-chip regulator. It is typically under software control and powered when wireless communications is required
•
The Radio power domain supplies the radio interface. It is powered during transmit and receive and controlled by the baseband processor.
16.2 Sleep Modes
Sleep modes enable the application to shut down unused functions in the device, thereby saving power. The JN5121 provides three sleep modes allowing the user to tailor the power consumption to the application’s requirements. The state of the JN5121 pins during sleep are described in section 2.2. The DIO pins retain their input or output status and their output value for the sleep period.
16.2.1 CPU Doze
Whilst in doze mode CPU operation is stopped but it remains powered and the digital peripherals continue to run. Doze mode is entered by executing the
vAHI_CpuDoze()
function and is terminated by any interrupt request. Once the interrupt service routine has been executed the
vAHI_CpuDoze()
function returns and normal program execution resumes. Doze mode uses more power than sleep and deep sleep modes but requires less time to restart and can therefore be used as a low power alternative to an idle loop.
16.2.2 Sleep
The JN5121 enters sleep under CPU control using the
vAHI_PowerDown()
function. All power domains are turned off except the VDD supply power domain and optionally the memory domain, determined by
vAHI_MemoryHold()
. A wakeup event, caused by an interrupt from the wakeup timers, DIO pins or analogue comparator inputs bring the device out of sleep. Wakeup from sleep is described in detail in section 16.3.
16.2.3 Deep Sleep
Deep sleep mode gives the lowest power consumption as all switchable power domains are off and functions in the VDD supply power domain, including the 32kHz oscillator are stopped. It is entered by executing the
vAHI_PowerDown()
function. This mode can only be exited by a power down or hardware reset on the RESETN pin. 46 JN-DS-JN5121 v1.8 © Jennic 2007 Preliminary
