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Text version of the page
| Jennie | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| Figure 19: Typical JN5121 SPI Peripheral Connection | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN5121 supports transfers at selectable data rates from 16MHz to 250kHz selected by a clock divider. Both SPICLK clock phase and polarity are configurable. The SPICLK line is held low when the interface is not being used. The clock phase determines which edge of SPICLK is used by the JN5121 to present new data on the SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. These options are specified using the vAHI_SpiConfigure() function. The slave select outputs, SPISELn, are controlled using the vAHI_SpiSelect() function. If more than one SPISEL line is to be used in a system they must be used in numerical order, for instance if 3 SPI select lines are to be used, they must be SPISEL0, 1 and 2. The number of SPISEL lines to be used in a system is controlled using vAHI_SpiConfigure(). A SPISEL line can be automatically deasserted between transactions if required, or it may stay asserted over a number of transactions until removed by a call to vAHI_SpiSelect(). For devices such as memories where a large amount of data can be received by the master by continually providing SPICLK transitions, the ability for the select line to stay asserted is an advantage since it keeps the slave enabled over the whole of the transfer. A transaction commences with the SPI bus being set to the correct configuration using vAHI_SpiConfigure(), and then the slave device being selected using vAHI_SpiSelect(). Transmit commences using the vAHI_SpiStartTransferxx() function (where xx is either 8, 16 or 32 bits) This will cause data to be placed in the FIFO data buffer and be clocked out, at the same time generating the corresponding SPICLK transitions. Since the transfer is full-duplex, the same number of data bits is being received from the slave as it transmits. The data that is received during this transmission can be read using u32AHI_SpiReadTransferxx() (again xx is either 8, 16 or 32 bits). If the master simply needs to provide a number of SPICLK transitions to allow data to be sent from a slave, it can perform a vAHI_SpiStartTransferxx() using dummy transmit data. An interrupt can be generated when the transaction has completed when enabled by vAHI_SpiConfigure(). Alternatively the interface can be polled using the bAHI_SpiPollBusy() or vAHI_SpiWaitBusy() functions. If a slave device wishes to signal the JN5121 indicating it has data to provide it may be connected to one of the DIO pins that can be enabled as an interrupt. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| JN-DS-JN5121 v1.8 Preliminary | © Jennic 2007 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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