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netX 50 –networX on chipThe future of communication

Description

Flexible “high end” networkcontroller with host interface or single chip solution for digital I/Os Two communication channels as Real-Time Ethernet with PHY or fieldbus
Supported Real-Time-Ethernet- Systems New system architecture optimized for communication and high data throughput 32-Bit / 200 MHz CPU ARM966 with 112 KB SRAM / 64 KB ROM and extensive periphery Dual-Port-Memory,Extension bus or digital I/Os IO-Link Controller, 8 channels CCD-Sensor Controller
The netX is a highly integrated network controllerwith a new system architecture optimized for com-munication and maximum data throughput.Via an integrated dual-port memory it works as ancompanion chip to a host CPU and realises thecomplete scope of industrial communication from fieldbus systems up to the Real-Time Ethernetsystems. Allows the application no own CPU thehost interface can be configured as Extension Bus or directly as digital input and output. The SupportedFieldbus-Systems Master only Slave only 32-BitCPU ARM966E-S is clocked with 200MHz and has 112 KB internal RAM and 64 KByteROM memory. The memory can be expanded fle-xible by the 32-Bit memory controller with SDRAM, SRAM or FLASH externally. Extensive periphery functions, serial interfacessuch as UART, USB, SPI, I²C, as well as the inte-grated IO-Link and CCD controller allows a largescope of applications. The central data switch and the free configurable communication channels with its own intelligenceare the unique selling proposition of the netX as an“high end” network controller. The data switch connects via five data paths to the ARM CPU and the communication, Host and DMAcontrollers with the memory or the peripheral units.In this way the controllers transmit their data in parallel, contrary to the traditional sequential archi- tecture with only one common data bus and addi-tional bus allocation cycles.The controllers of the two communication chan-nels are structured on two levels and are identicalto each other. They consist of dedicated ALUs and special logic units that receive their protocol func-tions via Microcode. For Ethernet the PHYs areintegrated which means that the external circuit for Ethernet is reduced to passive componets: trans-former and RC components. The Medium-Access-Controller xMAC sends or receives the data according to the respective busaccess process and encrypts or converts theseinto Byte depictions. The Protocol Execution Controller xPEC compiles these into data packets and controls the telegramtraffic. Large data amoutns are exchanged in DMAblocks over the memory of the ARM. In addition, every channel has a Dual-port-memory availablefor status information. Alternatively a triple bufferlogic is implemented for a conflict free data exchange which always gives the address of thenext free buffer. With the intelligent communication ALUs, the netXcarries out the most varied protocols and protocolcombinations on one chip – an absolutely new feature in industrial communication technology.