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Neuro-ASIC

Neuro-ASIC DANA23

General information The DANA23 ( D igital A daptive N euro A SIC) neurochip implements a universalneurocontroller. The chip contains a complete feed-forward network with integrated weight storage. Furthermore, there is also a modified back- propagation learning algorithm integrated into the ASIC. Architecture The neuro-ASIC features over 40 input elements and a total of 23 neurons.Twenty neurons can be configured as hidden neurons in one or two layers. At most, three neurons can be used as pure output neurons. All neurons have a quadratic activation function with variable steepness.Also integrated on the chip are: ? 260 synapses with adjustable 10-bit weight memory ? 23 bias registers ? 23 slope registers for adjustment of the activation function steepness ? a configuration register for variable structure of the network ? a register for adjustment of learning parameters ? 16-bit address/data bus , 4-bit control bus ? 84 inputs and outputs for cascading of three ASICs Block diagram
Neuronal Networks 10 - Bit - Parallel/Serial Converter (40) I/OController 10 - Bit - Serial/Parallel Converter (23) 10 - Bit - Weight Register (260) 10 - Bit - Bias Register (23) 16 - Bit - Configuration Register (8) 10 - Bit - Threshold Register (6) 4 - Bit - Slope Register (23) 23 164 AddressControl 16 Data Neural Network with 23 Neurons Hidden-Layer 1 40 12 Neurons Cascadable I/O 8 Output-Layer 31284 3 Neurons Hidden-Layer 2 8 Neurons