ASIC Solutions Brochure - Freescale - #4

Since today's integrated circuits incorporate more functionality, Freescale's ASPO offers greater services in addressing system-level requirements. Using our vast design engineering expertise, we develop ASIC and SoC design solutions from a system approach for each of our customers. Freescale enables successful design solutions by leveraging our IP portfolio, reusing the same modules and verification environment for our standard and ASIC products.

Freescale's design methodology uses a hierarchical and iterative approach designed to enable flexibility, fast turnarounds and first pass silicon success. Our team employs a rigorous design approach using block-level physical synthesis to optimize frequency and area while minimizing power through the support of multi-Vt transistors. Top-level netlist integration, clock-tree synthesis and scan insertion are designed incorporating customer inputs, and are completed meticulously by expert engineers and tool flows. Design accuracy is verified through electrical rules checking (ERC), formal

verification and design for test (DFT). Static timing analysis incorporating both signal integrity (SI) and on-chip variation (OCV) is a critical element of our methodology to ensure timing accuracy across a variety of manufacturing conditions. Power and IR drop analysis also guarantees optimal power routing for top performance while verifying power levels meet packaging, application and customer needs. Our comprehensive methodology addresses the reliability, maintainability and testability necessary for market leadership.

Flexible Processing Platform Options

Scalable Performance

Protocols

Security

Customer IP