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PF1192-03

S1R72803F00A *1 - 33943 S1R72803F00A

S1R72803F00A

IEEE1394 LINK / Transaction Controller

SBP-2 LINK Engine on chip High-speed transfer(Ultra ATA66)

P Preliminary

Built-in CPU and Flash DESCRIPTION

The S1R72803F00A is an IEEE Standard 1394-1995, P1394a Draft2.1 compliant LINK/Transaction Controller.Since some of the transaction functions of this controller have become hardware, the later PageTable fetch anddata transmission can be executed automatically by setting the PageTable address and size in SBP-2.In addition, thanks to a built-in MPU (SEIKO EPSON’s original 32-bit RISC processor S1C33) called a FlashROM which is necessary for the conversion system, the controller can provide peripheral devices with theoptimum 1394 interfaces by simply adding a Cable PHY Transceiver/Arbiter that complies with the standard.

FEATURES

LINK/Transaction Controller?All interactive data transmissions in both asynchronous and isochronous transfer modes are supported.?Stable interactive data transmissions of 100 Mbps, 200 Mbps and 400 Mbps of MaxPayload were madepossible by the built-in SRAM.?The hardware can detect IsocronousResourceManager automatically.?Some of the transaction functions have become hardware to prevent the actual data transmission ratefrom declining due to overhead (to secure the dedicated partition).?Communication with the upper layers has been simplified by separating the header and data partitions.?The data partition has been subdivided into Stream and ORB partitions. ?A ring buffer is employed for the recipient header, recipient data (recipient Stream and recipient ORBpartitions) and sending data partitions.?The sizes of all partitions can be set freely.?The busy state during data reception is controlled by the hardware automatically. SBP-2 SupportBy setting the PageTable address and size in SBP-2, the later Page Table fetch and data transmission canbe executed automatically. PHY/LINK InterfaceThe P1394a is supported. Transmission rate 100/200/400 Mbps are supported.Isolation is supported (a bus holder is built in). CPUSEIKO EPSON’s original 32-bit Microsoft Controller Unit is built in.Booting using both internal and external Flash ROMs is possible. IDE InterfacePIO mode 0/1/2/3/4, Multiword DMA mode 0/1/2 and Ultra-DMA mode 0/1/2/3/4 are supported. I/O baffer with 5V tolerance Built-in SRAMFor the data packet : 8-KbyteFor the MCU work : 8-Kbyte Built-in Flash ROMAn 64-Kbyte Flash ROM is built-in. 3.3 V/ 5.0 V power supply 184-pin flat package (Pin pitch: 0.4 mm) The package is not designed to be radiation-proof.
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