| ■ Highest pin bandwidth • 3.2Gbps, 4.0Gbps, 4.8Gbps Octal Data Rate (ODR) signaling • 3.2GHz, 4.0GHz, 4.8GHz data rate, octuple the system clock transfer rate of 400MHz, 500MHz, 600MHz • Bi-directional differential RSL (DRSL) • Flexible read / write bandwidth allocation • Minimum pin count • On-chip termination • Reduced system cost and routing complexity ■ Highest sustained bandwidth per DRAM device • 6.4GB/s, 8.0GB/s, 9.6GB/s peak data transfer rate • 8 banks: Bank-interleaved transactions at full bandwidth • Dynamic request scheduling • Early-read-after-write support for maximum efficiency • Zero overhead refresh ■ Low power • 1.8V VDD • Small-swing I/O signaling (DRSL) (200mV) • Power-down self-refresh support ■ Package • 104-ball FBGA 15. 1 8m m x 14. 56m m • Ball-pitch 1.27mm / 0.8mm |