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Fully Buffered DIMM - Brochure - Elpida Memory


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Fully Buffered DIMM
ELPIDA
Main Memory for Next Generation Servers
The Fully Buffered Dual in-line Memory Module (FB-DIMM) provides advanced performance for next-generation servers and adopts a Point-to-Point connection on the bus between the memory controller and the DIMM, as well as between the DIMMs themselves. FB-DIMMs were created to solve the performance limitations of Registered DIMMs that were the previous standard for server platforms. FB-DI MMs were designed to support next-generation processors an d faster bus speeds.
Elpida Mem ory will con tin ue to expan d its FB-DI MM lin eup an d provide DRAM products for high-en d systems.
Features of the Fully Buffered DIMM
In the new FB-DIMM, all signals — clock, address, command and data — to and from the DRAM on the module are buffered at the high-speed Advanced Memory Buffer (AMB) chip located on the DI MM. This helps to secure the DRAM tim in g m argin s during high-speed operation with a much shorter signal path between the DRAM and the AMB.
The FB-DI MM also adopts a Point-to-Point connection on the bus between the mem ory con troller and the DI MM, as well as between the DIMMs themselves. This allows increased bus speed with a shorter connection path. I t also greatly improves the maximum number of DIMMs that can be loaded on the bus — up to eight 2-rank DIMMs — with less concern about sign al degradation .
By comparison, existing standard Registered DIMMs have a stub-bus architecture along the mem ory bus between each DI MM and the memory controller. As the memory frequency increases, the controller must reduce the number of DIMMs loaded on the memory bus to secure the signal quality and the timing margin along the lengthy signal path between the DRAM devices on the module and the con troller on the motherboard. This limitation has presented a bottleneck in achieving improved performan ce in server application s where both high-speed and high-density are essential.
■ FB-DIMM
Point-to-Point architecture (Serial connection)
Up to 8 DIMMs can be loaded
■ Standard DIMM
Stub-bus architecture (Parallel connection)
Document No. E0632E80 (Ver.8.0) Date Published February 2007 (K) Japan Printed in Japan
© Elpida Memory, Inc. 2004-2007
http://www.elpida.com

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