DDR3 SDRAM - Brochure - Elpida Memory - #1

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Notes 1. ZQ Calibration: Calibrate DRAM ODT and Ron values over PVT (Process, Voltage, temperature). External resistor (240ohm±1%) is inserted between DRAM ZQ pin and GND for reference. To perform ZQ calibration, ZQCL or ZQCS command is used. (This is a self-calibration in which DDR3 performs all the measurement and adjustment automatically.)

2. OCD (Off Chip Driver Calibration): Calibrate DRAM Ron over PVT. External device connected to DRAM performs impedance measurement and adjustment (Not a self-calibration). OCD is an optional feature in DDR2.

3. /RESET pin is introduced in DDR3 for system stability. /RESET is active-low signal.

4. Dynamic ODT: ODT value during WRITEs can be changed dynamically by enable the Dynamic ODT mode in advance by MRS command. As a result, SI is improved.

5. DDR3 DIMM uses fly-by topology for CMD/ADD/CLK signals to improve SI. This causes flight time difference between DQ/DM/DQS and ADD/CMD/CLK. DDR3 has de-skew mechanism to compensate flight time difference.

Elpida Memory has developed a top-tier power efficient 1 Gigabit DDR3 SDRAM, which is capable of operating at an ultra-fast speed of 2Gbps.

This product uses 35% less operating current compared with the company's existing products and can support an operating speed of 2Gbps, which is considerably faster than the industry standard of 1600Mbps at 1.5V. Also, in response to demand for next-generation low-power products Elpida's new device can operate at 1600Mbps using 1.35V.

Elpida's new DDR3 SDRAM is based on advanced 65nm process technology. Sample shipments will start in September 2008 with mass production expected to begin the next month in October.