DDR SDRAM EM42BM1684RTA - eGismos - #1

/ 19


catalogue search
DDR SDRAM EM42BM1684RTA - eGismos
P. 01
DDR SDRAM EM42BM1684RTA - eGismos
P. 02
DDR SDRAM EM42BM1684RTA - eGismos
P. 03
DDR SDRAM EM42BM1684RTA - eGismos
P. 04
DDR SDRAM EM42BM1684RTA - eGismos
P. 05
DDR SDRAM EM42BM1684RTA - eGismos
P. 06
DDR SDRAM EM42BM1684RTA - eGismos
P. 07
DDR SDRAM EM42BM1684RTA - eGismos
P. 08
DDR SDRAM EM42BM1684RTA - eGismos
P. 09
DDR SDRAM EM42BM1684RTA - eGismos
P. 10
DDR SDRAM EM42BM1684RTA - eGismos
P. 11
DDR SDRAM EM42BM1684RTA - eGismos
P. 12
DDR SDRAM EM42BM1684RTA - eGismos
P. 13
DDR SDRAM EM42BM1684RTA - eGismos
P. 14
DDR SDRAM EM42BM1684RTA - eGismos
P. 15
DDR SDRAM EM42BM1684RTA - eGismos
P. 16
DDR SDRAM EM42BM1684RTA - eGismos
P. 17
DDR SDRAM EM42BM1684RTA - eGismos
P. 18
DDR SDRAM EM42BM1684RTA - eGismos
P. 19
Pages:
DDR SDRAM EM42BM1684RTA - eGismos


See other catalogues for eGismos
You may also be interested in

Power supply controller, Controller, Memory, DRAM, RAM


Text version of the page

EM42BM1684RTA

512Mb (8M ×××× 4Bank ×××× 16) Double DATA RATE SDRAM

Features Description

• Internal Double-Date-Rate architecture with 2 Accesses per clock cycle. • Single 2.5V The EM42BM1684RTA is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8Meg words x 4 banks by 16 bits. The 512Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins. Available packages:TSOPII 66P 400mil. ± 0.2V Power Supply • 2.5V SSTL-2 compatible I/O • Burst Length (B/L) of 2, 4, 8 • 2,2.5,3 Clock read latency • Bi-directional,intermittent data strobe(DQS) • All inputs except data and DM are sampled at the positive edge of the system clock. • Data Mask (DM) for write data • Sequential & Interleaved Burst type available • Auto Precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • DLL aligns DQ & DQS transitions with CLK transition • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms

Ordering Information

Part No Organization Max. Freq Package Grade Pb

EM42BM1684RTA-75F 32M X 16 133MHz @CL25 66pin TSOP(ll) Commercial Free EM42BM1684RTA-6F 32M X 16 166MHz @CL25 66pin TSOP(ll) Commercial Free EM42BM1684RTA-5F 32M X 16 200MHz @CL3 66pin TSOP(ll) Commercial Free * EOREX reserves the right to change products or specification without notice.
Jul. 2006 www.eorex.com 1/19

pageCatalog pdf di En 2012-05-22-29