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Specifications

Product TypeFPGA Resources Memory Clocks Data Rates Data Format (I/O)PCI Express Compliance Connectors CablingPhysical Environmental System and Software PCIe8 LX is a PCI Express 8-lane main board; it supplies DMA, memory, and programmable FPGA resources to a mezzanine board.One programmable FPGA (Xilinx Virtex 5 LXT XC5VLX110T or optional 220T or 330T) SRAM 8 MB DRAM (DDR2) 0 or optional 1 GB or 2 GB 200-pin SODIMMFour programmable independent PLL clock generators, each with input and output clocks: Input (reference) clocks can be set to 10.3681 or 40 MHz, or PCIe clock. Output clocks can be set with only +/- 50 ppm error to 1.544, 2.048, 6.312, 8.448, 34.368, or 44.736 MHz.Peak 1.6 GB/s Typical TBD (dependent on mezzanine board, bus chipset, and host system)Determined by mezzanine board and optional auxiliary boardPCIe version PCIe 1.1 DMA Up to 16 channels, depending on mezzanine board Number of lanes 8Five CMC-type (IEEE 1386) mezzanine 221 LVTTL I/O (mate to AMP 120527-1 or Molex 71436-2164) One 6-pin .100” x 1 row square .025” For FPGA JTAG (IEEE 1149.1) One 8-pin .100” x 1 row square .025” square pins For six external debugging LEDs One 40-pin ATA-type expansion 30 LVTTL signals for external board or FPGA debugging (8 can be used for Xilinx RocketIO)Consult EDT for purchase options.Weight 3.9 oz. typical Dimensions 6.6 x 4.2 x 0.5 in.Temperature Operating 0° to 40° C Non-operating -40° to 70° C Humidity Operating 1% to 90%, non-condensing at 40° C Non-operating 95%, non-condensing at 45° CSystem must have a PCI Express slot (8 or 16 lanes). Software is included for Windows, Solaris, Linux, and Mac OS X and can be requested for VxWorks; for versions, see our website.

Ordering Options

- Mezzanine board: See Compatibility Guide. - FPGA: XC5VLX 110T / 220T / 330T - DRAM: Bold is default. For more options, see mezzanine board datasheet. / 1 GB / 2 GB Ask about custom options. 39