2008-2009 Telemetry / Telecom series catalog - EDT - #37

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Specifications

Product TypeFPGA Resources Memory Clocks Data Rates Data Format (I/O)PCI Compliance Connectors CablingPhysical Environmental System and Software PCI SS is a PCI main board; it supplies DMA, memory, and programmable FPGA resources to a mezzanine board.One programmable FPGA (Xilinx Virtex XCV1000E or optional 2000E or 600E) SRAM (with HRC or OCM mezzanine board) One bank of 256 K x 36 (1 MB total) or optional 512 K x 36 (2 MB total) or optional 1 M x 36 (4 MB total) or optional 0 SRAM (with any other mezzanine board) Two banks of 256 K x 36 (1 MB per bank; 2 MB total) or optional 512 K x 36 (2 MB per bank; 4 MB total) or optional 1 M x 36 (4 MB per bank; 8 MB total) or optional 0 DRAM 0Four programmable independent PLL clock generators, each with input and output clocks: Input (reference) clocks can be set to 10.3681 or 40 MHz, or PCI clock. Output clocks can be set with only +/- 50 ppm error to 1.544, 2.048, 6.312, 8.448, 34.368, or 44.736 MHz.Peak TBD Typical TBD (dependent on mezzanine board, bus chipset, and host system) Determined by mezzanine board and optional auxiliary boardPCI version PCI 2.3 DMA 1, 4, or 16 channels, depending on mezzanine board Number of slots 1Five CMC-type (IEEE 1386) mezzanine 221 LVTTL I/O (mate to AMP 120527-1 or Molex 71436-2164) One 8-pin .100” x 1 row square .025” square pins For six external debugging LEDs One 40-pin ATA-type expansion 30 LVTTL signals for external board or FPGA debuggingConsult EDT for purchase options.Weight 3.3 oz. typical Dimensions 6.6 x 4.2 x 0.5 in.Temperature Operating 0° to 40° C Non-operating -40° to 70° C Humidity Operating 1% to 90%, non-condensing at 40° C Non-operating 95%, non-condensing at 45° CSystem must have a PCI or PCI-X slot, 32- or 64-bit and 66 MHz or faster (33 MHz will work, but at reduced data rates). Software is included for Windows, Solaris, Linux, and Mac OS X and can be requested for VxWorks; for versions, see our website.

Ordering Options

- Mezzanine board: See Compatibility Guide. - FPGA: XCV 1000E / 2000E / 600E - SRAM: Up to 8 MB (options above) Bold is default. For more options, see mezzanine board datasheet. Ask about custom options. 35

pageCatalog pdf di En 2012-02-07-16