Neuron Chip Network Processor - Cypress Semiconductor - #1

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CY7C53150, CY7C53120 Neuron Chip Network Processor Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-10001 Rev. *G Revised March 26, 2010 Features �¡ Three 8-bit pipelined processors for concurrent processing of application code and network traffic �¡ 11-pin I/O port programmable in 34 modes for fast application program development �¡ Two 16-bit timer/counters for measuring and generating I/O device waveforms �¡ 5-pin communication port that supports direct connect and network transceiver interfaces �¡ Programmable pull ups on IO4–IO7 and 20 mA sink current on IO0–IO3 �¡ Unique 48-bit ID number in every device to facilitate network installation and management �¡ Low operating current; sleep mode operation for reduced current consumption[1] �¡ 0.35 ìm Flash process technology �¡ 5.0V operation �¡ On-chip LVD circuit to prevent nonvolatile memory corruption during voltage drops �¡ 2,048 bytes of SRAM for buffering network data, system, and application data storage �¡ 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2), 4096 bytes (CY7C53120E4) of Flash memory with on-chip charge pump for flexible storage of configuration data and application code �¡ Addresses up to 58 KB of external memory (CY7C53150) �¡ 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM containing LonTalk network protocol firmware �¡ Maximum input clock operation of 20 MHz (CY7C53150), 10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a –40°C to 85°C[2] temperature range �¡ 64-pin TQFP package (CY7C53150) �¡ 32-pin SOIC or 44-pin TQFP package (CY7C53120) Notes 1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. See the Neuron Technical Reference Manual for more details. 2. Maximum Junction Temperature is 105°C. TJunction = TAmbient + V•I•èJA. 32-pin SOIC èJA = 51C/W. 44-pin TQFP èJA = 43C/W. 64-pin TQFP èJA = 44C/W. Media Access Control Processor Network Processor Application Processor 2 KB RAM Communications Port I/O Block 2 Timer/ Counters Oscillator, Clock, and ROM Internal Data Bus (0:7) Address Bus (0:15) Control Internal CP4 CP0 IO10 IO0 CLK1 CLK2 SERVICE RESET External Address/Data Bus Flash (CY7C53120) (CY7C53150) Logic Block Diagram [+] Feedback