High Accuracy EPROM Programmable PLL Die for Crystal Oscillators - Cypress Semiconductor - #1

Text version of the page

CY2037 High Accuracy EPROM Programmable PLL Die for Crystal Oscillators Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-07354 Rev. *J Revised October 25, 2010 igh Accuracy EPROM Programmable PLL Die for Crystal Oscillators Features �¡ Erasable programmable read only memory (EPROM) - programmable die for in-package programming of crystal oscillators �¡ High resolution Phase locked loop (PLL) with 12-bit multiplier and 10-bit divider �¡ EPROM programmable capacitor tuning array with optional shadow register �¡ Twice programmable die �¡ Simple 2-wire programming interface �¡ On-chip oscillator runs from 10 MHz to 30 MHz fundamental tuned crystal �¡ EPROM-selectable Transistor transistor logic (TTL) or Complementary metal oxide semiconductor (CMOS) duty cycle levels �¡ Operating frequency: 1 MHz to 133 MHz at 5 V 1 MHz to 100 MHz at 3.3 V 1 MHz to 66.6 MHz at 2.7 V �¡ Eight selectable post divide options, using PLL or reference oscillator output �¡ Programmable asynchronous or synchronous OE and power-down (PD#) modes(CY2037 and CY2037-2) �¡ Frequency select (CY2037-3) �¡ Low jitter outputs typically: 33 MHz 33 MHz �¡ 3.3 V or 5 V operation �¡ Small die �¡ Controlled rise and fall times and output slew rate Functional Description CY2037 is an EPROM-programmable, high accuracy, PLL-based die designed for the crystal oscillator market. The die attaches directly to a low cost 10 to 30 MHz crystal and can be packaged into a 4-pin through-hole or surface mount packages. The oscillator devices may be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. CY2037 contains an on-chip oscillator and a unique oscillator tuning circuit for fine-tuning of the output frequency. The crystal Cload may be selectively adjusted by programming a set of seven EPROM bits. This feature is used to compensate for crystal variations or to obtain a more accurate synthesized frequency. CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes VSS and VDD. Clock outputs may be generated up to 133 MHz at 5 V or up to 100 MHz at 3.3 V. The entire configuration can be reprogrammed once, which allows the programmed inventory to be altered or reused. CY2037 PLL die is designed for very high resolution. It has a 12-bit feedback counter multiplier and a 10-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM error. The clock is further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64, and 128. The divider input can be selected as the PLL or crystal oscillator output, providing a total of 16 separate output options. For further flexibility, the ouput is selectable between TTL and CMOS duty cycle levels. CY2037 also contain flexible power management controls. These parts include both power down (PD#) and output enable (OE) features with integrated pull-up resistors. The PD# and OE modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. When PD# or OE modes are enabled, CLKOUT is tri-stated and pulled low by a weak pull-down. In PD# mode, all active circuitry on chip get shutdown, where in OE mode PLL and oscillator remain operating. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable CY2037 to have low jitter and accurate outputs, making it suitable for most PC, networking, and consumer applications. On the other hand, CY2037-3 contains a frequency select function in place of the power-down and output enable modes. For example, consumer products often require frequency compatibility with different electrical standards around the world. With this frequency select feature, a product that incorporates CY2037-3 could be compatible with both NTSC for North American, and PAL for Europe by simply changing the FS line. The twice programmable feature is absent in CY2037-3, because the second EPROM row is now being used for the alternate frequency. Table 1. Device Functionality: Output Frequencies Parameter Description Condition Min Max Unit Fo Output frequency VDD = 4.5 V to 5.5 V 1 133 MHz VDD = 3.0 V to 3.6 V 1 100 MHz VDD = 2.7 V to 3.0 V 1 66 MHz [+] Feedback