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| | | IDM 1553 | | |
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| | | Table 5 IDM1553 - XX - XD PIN-OUT (DUAL-IN-LINE PACKAGE) | | |
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| | | | | | | | | | | | PIN | NAME | TYPE | FUNCTIONAL DESCRIPTION | | | | 1 | DO | I/O | DATA BUS BIT 0 | | | | 2 | D2 | I/O | DATA BUS BIT 2 | | | | 3 | D4 | I/O | DATA BUS BIT 4 | | | | 4 | D6 | I/O | DATA BUS BIT 6 | | | | 5 | D8 | I/O | DATA BUS BIT 8 | | | | 6 | D10 | I/O | DATA BUS BIT 10 | | | | 7 | D12 | I/O | DATA BUS BIT 12 | | | | co | D14 | I/O | DATA BUS BIT 14 | | | | 9 | TA1 | I | TERMINAL ADDRESS BIT 1 | | | | 10 | TAO | I | TERMINAL ADDRESS BIT 0 | | | | 11 | TA4 | I | TERMINAL ADDRESS BIT 4 | | | | 12 | THARD | I | HARDWIRED TERMINAL ADDRESS SELECT IF HIGH | | | | 13 | WTDGBRES | 0 | EXTERNAL WATCHDOG TIMER RESET ON BUS B | | | | 14 | Voce | | +5V SUPPLY FOR DIGITAL LOGIC CIRCUITRY | | | | 15 | BR | I/O | BUS REQUEST. USED FOR DMA OPERATION | | | | 16 | BGACK | I/O | BUS GRANT ACKNOWLEDGE. USED IN DMA MODE | | | | 17 | PHI1 | 0 | 8MHz CLOCK OUT - PHASE 1 | | | | 18 | Vs*b | | RESERVED FOR -15V TO BUS B TRANSCEIVER | | | | 19 | GND B | | GROUND TO BUS B TRANSCEIVER | | | | 20 | BUS B | | TRANSCEIVER B BUS SIGNAL (TRUE) TO THE TRANSFORMER ON 1553 CHANNEL B | | | | 21 | LOGIC GND | | GROUND FOR THE DIGITAL LOGIC CIRCUITRY | | | | 22 | A1 | I/O | ADDRESS BIT 1 | | | | 23 | A3 | I/O | ADDRESS BIT3 | | | | 24 | A5 | I/O | ADDRESS BIT 5 | | | | 25 | A7 | I/O | ADDRESS BIT 7 | | | | 26 | A9 | I/O | ADDRESS BIT 9 | | | | 27 | A11 | I/O | ADDRESS BIT 11 | | | | 28 | A13 | 0 | ADDRESS BIT 13 | | | | 29 | A15 | 0 | ADDRESS BIT 15 | | | | 30 | DMA/DPR | I | DMA OR DUAL CONFIGURATION SELECT. HIGH - DMA MODE, LOW - DUAL PORT MODE | | | | 31 | MEMCSOUT | 0 | MEMORY CHIP SELECT OUT MAY BE CONNECTED TO MEMCSUIN AND MEMCSLIN OR TO EXTERNAL MEMORY | | | | 32 | CLK32 | I | 32 MHz CLOCK INPUT | | | | 33 | CREG | I | INTERNAL REGISTER SELECT LINE FROM CPU | | | | 34 | SLOW | I | SLOW CLOCK. WHEN HIGH A 16MHz CLOCK CAN BE USED BUT MEMORY ACCESS TIME IS INCREASED. (C-MAC TEST PIN ONLY) | | | | 35 | TXINHA | I | TRANSMITTER INHIBIT A FROM EXTERNAL WATCHDOG TIMER | | | | 36 | CR/W | 1 | READ/WRITE LINE FROM CPU (DUAL PORT MODE). HIGH - READ, LOW - WRITE | | | | 37 | WTDGARES | 0 | EXTERNAL WATCHDOG TIMER RESET ON BUS A | | | | 38 | GND A | | GROUND TO BUS A TRANSCEIVER | | | | 39 | VSNA | | RESERVED FOR -15V TO BUS A TRANSCEIVER | | | | | | | | | | | |
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| | | Table continued overleaf | | |
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