Power Architecture 405EXr processor

Specifications

1 LanePCIExpress 16/32bitw/ECC 4 ExternalChannels OPBPLB4Bridge
ExternalBusController

CPU Complex

HSS x1

Power Architecture 405 processor coreUp to 533 MHz/810 DMIPS 16KB I-cache/16KB D-cache

DDR1/2SDRAMController DMAController PLB4OPBBridge
NANDFlash Ctrl PCIe PCIe IntHandler

Memory and Bus Architecture

100MHzMax.On-ChipPeripheralBus(OPB) EBM

32-bit DDR1/2 SDRAM controller with ECC, supports both x16 or x32, up to 2GB memory bankExternal Bus Master Interface (EBMI) 8/16/32-bit External Peripheral Bus Controller NAND Flash controller

PLB4 128b200MHzmax – 12masters - 2-way crossbar

UARTs TurboSecurityEngine TRNGPKA MAL
IICs 16KI-Cache16KD-Cache

System Resources

Universal Interrupt Controller: 10 external interrupts Up to 32 general purpose I/Os DMA Controller with four independent channels

MMU USB2.0OTG
GPIOs 10/100/1GEthernetMAC 405 CPU
GPT

High Speed & Inter-Chip Connectivity

JTAG Trace UIC
Sys,DDR PLLs,UARTSer Clocks

One PCI Express 1-Lane Interface with controller and SERDES, up to 2.5Gbps

PowerPC 405 Core333-533 MHz

ULPI SDRInterface RGMIIor GMII
SPI

Network Connectivity

One 10/100/1G Ethernet MACUSB2.0 On-the-Go port, both host and device mode supported Two UARTs

PPC405EXr-SSC533T

AMCC Part Name Special Functionality Security S = Security N = No SecurityProcessor Speed 333, 400 and 533 MHz

Turbo Security Engine: Optional on-chip IPSec/SSL/bulk data security acceleration engine (Crypto Engine)

Package (EPBGA) P = 27mm S = 27mm lead-freeCase Temperature Range T = -40C to 85CRevision Level C = 1.2 Power

1.3W est. typical power @ 400 MHz CPU •• •••• ••• •••• •••

(Part number preliminary and subject to change)

Target Applications

WLAN Access - 802.11n WAP applications for small or medium businesses, IP-STB’s or residential gateways, and high-end SOHO•WiMAX CPE, either xed or mobileGeneral Networking General Purpose processing•• •