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Power Architecture 405CR processor

Specifications

133MHz13-Bit address 32-Bit data66MHz32-Bit address 32-Bit data

CPU Complex Power Architecture 405 processor coreUp to 266 MHz/404 DMIPS 16KB I-cache/8KB D-cache

SDRAMController
ExternalBusController IIC Code Decompression

Memory and Bus Architecture

UART

On-chip SDRAM controller with ECC Option On-chip external bus controller

Arbiter

Processor Local Bus (PLB)133MHz 64-Bit

System Resources

UART

Up to 23 general purpose I/Os On-chip DMA controller

16KI-Cache8KD-Cache
GPIO

High Speed & Inter-Chip Connectivity

DMAControllerOPBBridge

Master and slave IIC controller

MMU
On-ChipPeripheralBus(OPB)66MHz

Network Connectivity

405 CPU
Timers

Two UARTs

JTAG Trace InterruptController

Power

Arbiter

0.8W typical power @ 200 MHz •• •••••• • •

PowerPC 405 Core

PPC405CR-3BC200CZ

AMCC Part NameShipping Package z = tape/reel blank=tray Revision Level C = 2.1 Case Temperature Range C = -40C to 85CProcessor Speed 133, 200 and 266 MHzGrade 3 ReliabilityPackage (EPBGA) B = 27mm K = 27mm lead free H = 27mm low soft error rate (SER)

Target Applications

Wired communications •Data storage •Pervasive computing devices •