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Power Architecture 440SPe processor

Specifications

MII/GMII

ExternalBusController

CPU Complex

PowerPC 440 Core

InterruptControllerOPBBridge 10/100/GEthernet

Power Architecture 440 processor coreUp to 800 MHz/1600 DMIPS 32KB I-cache/D-cache with parity 256KB L2 cache, may also be used as on-chip SRAM

32KI-Cache32KD-Cache PCI-EIRQHandler
UART (3) I2O/DMAController XOR/DMA MAL

Memory and Bus Architecture

256KBL2 Cache/SRAM IIC (2)

128-bit, 166 MHz, 2-way Crossbar Processor Local Bus supporting 10.4GB/sec. peak bandwidthDual-ported 32/64-bit SDRAM memory controller, interfaced to both PLB slave segments, supporting 166/333 MHz DDR1 and 333/667 MHz DDR232-bit, 83 MHz external bus controller

Up to 166MHz

2-Way Processor Local Bus (PLB)128-Bit 64-Bit

GPIO (32)

Low Latency Slave SegmentHighBandwidth Slave Segment

System Resources

Timers On-ChipPeripheralBus(OPB)Upto83MHz

Up to 32 general purpose I/Os Two-channel DMA included with I2O; One-channel DMA with XOR

DDR1/2SDRAM PCI Express PCI Express4 PCI Express4 PCI-X DDR

High Speed & Inter-Chip Connectivity

System LogicClocks, PWR MgtTrace/PLLs

PCI-Express ports - one “x8” lane and two “x4” lane PCI-X interface supporting DDR Operation Master and slave IIC controller

64/32-Bit 8 Lanes Lanes Lanes 64-Bit

Network Connectivity

PPC440SPe-ANB533C

10/100/1G Ethernet MAC (GMII/MII) Three UARTs

AMCC Part Name Special Functionality RAID 6 A = No R = YesPackage (FC-PBGA) G =27mm N =27mm lead freeProcessor Speed 533, 667 and 800 MHzCase Temperature Range C = 0C to 95CRevision Level B = 2.0

RAID 5 and RAID 6 acceleration hardware RAID XOR function with one-channel DMA for parity generation and checking

Power

<7W typical power @ 533 MHz •• • ••• ••••• ••••••

Target Applications

RAID controllersStorage Area Networking (SAN) equipment••Network Attached Storage (NAS)Disk/Tape Backup Storage Equipment••