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ADA4961
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Catalog excerpts

ADA4961 - 1

Preliminary Technical Data FEATURES High speed −3 dB bandwidth: 2.5 GHz −1 dB bandwidth: 1.8 GHz Slew rate: 12 V/ns Settling time to 0.1%: TBD ns Overdrive recovery: TBD ns Digitally adjustable gain Voltage gain: −6 dB to +15 dB Power gain: −3 dB to +18 dB 5-bit parallel or SPI bus gain control with fast attack IMD3/HD3 distortion IMD3 at 1 GHz: −90 dBc HD3 at 500 MHz: −82 dBc HD3 at 1 GHz: −80 dBc HD3 at 1.5 GHz: −75 dBc Low noise Noise density RTO: 6.9 nV/√Hz Noise figure: 5.6 dB at G = +15 dB Differential impedances: 100 Ω input, 50 Ω output Low power mode operation Power-down control Single 3.3 V or 5 V supply operation Available in 24-lead, 4 mm × 4 mm LFSCP APPLICATIONS ADC driver for 12-bit to 14-bit Gs/s converters RF/IF gain block Line driver Instrumentation Satellite communications Data acquisition Military systems GENERAL DESCRIPTION The ADA4961 is a high performance BiCMOS RF differential amplifier (DGA) optimized for driving heavy loads out to 2.0 GHz and beyond. It typically achieves −90 dBc IMD3 performance at 500 MHz and −85 dBc at 1.5 GHz. The device also exhibits very low output noise (6.8nv/√Hz). Together, these performance numbers result in an SFDR of 133 dB/Hz at 1.5 GHz and set a new benchmark for dynamic range for the power consumed. This RF performance now allows GHz converters to achieve their optimum performance with minimal limitations of the driver amplifier or constraints on overall power that typically result from GaAs amplifiers. This product can easily drive 10-bit to 16-bit HS converters. Rev. PrB FUNCTIONAL BLOCK DIAGRAM In addition, for many receiver applications, antialias filter (AAF) designs may be simplified or not required. The ADA4961 has an internal differential input impedance of 100 Ω and a differential dynamic output impedance of 50 Ω, eliminating the need for external termination resistors. The digital adjustability provides for 1 dB resolution, thus optimizing SNR for input levels spanning 21 dB. The ADA4961 is optimized for wideband, low distortion performance at frequencies up to 1.5 GHz. These attributes, together with its wide gain adjustment and relatively low power, make it the amplifier of choice for many high speed applications, including IF, RF, and broadband applications where dynamic range at very high frequencies is critical. The ADA4961 is ideally suited for driving not only ADCs, but also mixers, pin diode attenuators, SAW filters, and multi-element discrete devices. It is available in a 4 mm × 4 mm, 24-lead LFCSP and operates over a temperature range of −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

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ADA4961 - 2

Preliminary Technical Data

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ADA4961 - 3

Preliminary Technical Data SPECIFICATIONS VS = 5 V, RS = 100 Ω differential, RL = 50 Ω differential, TA = 25°C, f = 500 MHz, VO = 1.2 V p-p (or 0.6 V p-p per tone for two tone IMD3), unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth −1 dB Bandwidth Slew Rate Settling Time to 0.1% Overdrive Recovery Time Input Return Loss (S11) Output Return Loss (S22) GAIN Maximum Voltage Gain1 Minimum Voltage Gain1 Gain Step Size Gain Step Error INPUT STAGE Input Common-Mode Voltage Input Resistance Maximum AC-Coupled Input Level Input Capacitance CMRR OUTPUT STAGE Maximum...

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ADA4961 - 4

Preliminary Technical Data VS = 5 V, RS = 100 Ω differential, RL = 50 Ω differential, TA = 25°C, f = 500 MHz, VO = 1.2 V p-p (or 0.6 V p-p per tone for two tone IMD3), unless otherwise noted. Table 2. Noise/Harmonic Performance Parameter GAIN AT 100 MHz Second Harmonic (HD2) Third Harmonic (HD3) Third-Order Intermodulation Distortion 1 dB Compression Point (OP1dB) Noise Figure (NF) GAIN AT 500 MHz Second Harmonic (HD2) Third Harmonic (HD3) Third-Order Intermodulation Distortion 1 dB Compression Point (OP1dB) Noise Figure (NF) GAIN AT 1000 MHz Second Harmonic (HD2) Third Harmonic (HD3)...

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ADA4961 - 5

Preliminary Technical Data DIGITAL SPECIFICATIONS Table 3. Serial Port Interface Timing Parameter Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Serial Clock Period Setup Time Between Data and Rising Edge of SCLK Hold Time Between Data and Rising Edge of SCLK Setup Time Between Falling Edge of CS and SCLK Hold Time Between Rising Edge of CS and SCLK Minimum Period SCLK Can Be in Logic High State Minimum Period SCLK Can Be in Logic Low State Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for a Read Operation Maximum Time Delay Between CS...

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ADA4961 - 6

Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Internal Power Dissipation 9JA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may...

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ADA4961 - 7

Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Mnemonic GND VIN+ VIN− MODE SDIO A4/CLK A3/CS A2/FA A1 A0 LATCH NC VOUT− VOUT+ PWUP LP Description Power Supply Ground. Connect to system ground plane. Noninverting Input. Inverting Input. Mode Select Pin for Gain Control. Low = serial (SPI), and high (3.3V) = parallel. Serial Data I/O Pin for SPI Gain Control. Bit A4 for Parallel Gain Control/Serial Clock Pin for SPI Gain Control. Bit A3 for Parallel Gain Control/Chip Select pin for SPI Gain Control. Bit A2 for Parallel Gain Control/Fast Attack pin for SPI Gain Control....

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