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Agilent J-BERT M8020A

Agilent J-BERT M8020A
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Agilent J-BERT M8020A High-Performance BERT Master Your Next Designs Data Sheet Version 1.0 Key features: • Data rates up to 8.5 and 16 Gb/s expandable to 32 Gb/s • 1 to 4 BERT channels in a 5-slot AXIe chassis • Integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, sinusoidal level interference (common-mode and differential-mode), SSC (triangular and arbitrary, residual) and Clock/2 • 8 tap de-emphasis, positive and negative • Interactive link training for PCI Express • Built-in clock recovery and equalization Description The high-performance Agilent J-BERT M8020A enables fast and accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s. With today’s highest level of integration, the M8020A streamlines your test setup. In addition, automated in situ calibration of signal conditions ensures accurate and repeatable measurements. And, through interactive link training, it can behave like your DUT’s link partner. All in all, the J-BERT M8020A will accelerate insight into your design.

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M8000 Series of BER Test Solutions Simplified time-efficient testing is essential when you are developing next-generation computer, consumer, or communication devices. The Agilent M8000 Series is a highly integrated BER test solution for physical layer characterization, validation, and compliance testing. With support for a wide range of data rates and standards, the M8000 Series provides accurate, reliable results that accelerate your insight into the performance margins of high-speed digital devices. Shift into high gear with the M8000 Series and take the design verification express lane....

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J-BERT M8020A high-performance BERT Enabling fast, accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s. Highest level of integration for streamlined test setups With J-BERT M8020A all receiver (RX) test capabilities are built-in: jitter sources, common- and differential-mode level interference, and de-emphasis to emulate the transmitter (TX) of the device under test (DUT). In addition M8020A provides a built-in reference clock multiplier for synchronization of the BERT pattern generator with the DUT’s reference clock which can carry spread...

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In situ calibration for the most accurate and repeatable results At data rates above 5 Gb/s, the influence of the channel (PC-board, cable, connectors) between transmitter (TX) and receiver (RX) is no longer negligible. The reference point for the RX specification moves to the RX input, the test set-up typically has to contain a certain channel characteristic, often an ISI channel, as well. To accurately inject a defined stress condition to the RX in situ calibration is required: at that same exact point where the receiver under test has to be connected during test, a reference load is...

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Figure 4. J-BERT M8020A high-performance BERT for accelerated receiver characterization. The configuration shows a 4 channel 16 Gb/s BERT in a 5-slot AXIe chasssis consisting of one M8041A module with two BERT channels and clock synthesizer and one M8051A extender module with two additional BERT channels. Applications R&D and test engineers who characterize and verify compliance of chips, devices, boards and systems with serial I/O ports up to 16 Gb/s. The M8020A can be used to test popular serial bus standards, such as PCI Express®, SATA/SAS, DisplayPort, USB Super Speed, MIPI M-PHY, SD...

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User interface and measurements File Application System Clock Generator Analyzer Patterns Measurements Utilities Window Help System View X jq^2- Error Ratio 1 Output Timing 1 \*~ Jitter Tolerance 1 «t litter Tolerance Template Editor 1 Sequence Editor* Pattern Editor Status Indicators Module Channel LF Jitter I Sweep Interfereno Preset Register Post-Cu rsorl Post-Cu rsorl Defines the post cursor 1 of a deemphasis Jitter Data CDR Unlock Data Loss Symbol Loss Sync Loss Output Jitter 5SC (Stopped) <Clk Loss Figure 5: The graphical user interface for J-BERT M8020A offers multiple views that can...

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Fife Setup Measure Tools Apps Help SIT: l* Rate: 31.W9941 Gfc/s PaL Length: 327C.7 Figure 7. The 32 Gb/s output signal shows excellent intrinsic jitter. This shows the output signal of M806IA when used with M804IA BERT module and its internal clock source and PRBS 2 '6- / pattern.

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Specifications for M8041A and M8051A J-BERT high-performance BERT modules Figure 8: Front panel view of M8041A module (bottom) and M8051A (top).

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Specifications pattern generator Data output (DATA OUT 1, DATA OUT 2) Table 1. Data output characteristics for M8041A and M8051A. All timing parameters are measured 0.5 V into ground Data rate Data format 1 or 2 (second channel requires opt. 0G2) 50 mV to 1.2 Vpp single ended, 100 mV to 2.4 Vpp differential, 1 mV resolution; addresses LVDS, CML, low-voltage CMOS, others. See table 2 for max. output amplitude in presence of CMI or DMI Amplitude accuracy Output voltage window External termination voltage -1 V to +3.0 V. For offset > 1.3 V the termination voltage should be ± 0.5 V of offset...

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Table 2. Data output amplitude maximum (single ended) in presence of DMI, CMI, offset voltage. Offset < 1.9 V De-emphasis (DATA OUT) M8020A provides built-in de-emphasis with positive and negative cursors based on a finite impulse response (FIR) filter. Table 3. Specifications for multi-tap de-emphasis (requires option 0G4). M8041A De-emphasis taps 8 (requires opt. 0G4) can be adjusted for each channel independently 1. Sum of all cursors may not exceed Vpp max. The tap accuracy applies for PCIe 3 presets for pre-cursor 1 and post-cursor 1 at 8 Gb/s. Post-cursor 1 = 20log10 Vb/Va Pe-cursor =...

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Table 4. Clock output specifications (M8041A only). Frequency range Frequency resolution Frequency accuracy 0.1 to 1 V, 5 mV steps, single ended Output voltage window External termination voltage Transition times Duty cycle Clock divider For other dividers use TRG output Clock modes Intrinsic random jitter 300 fs rms typical at 16.2 GHz and clock divider = 1 • 85 dBc/ Hz typical at 10 kHz offset and internal clock and 10/100MHz as external reference clock. • 80 dBc/Hz with 10 kHz offset for reference clock multiplier bandwidth 50 Q into GND or external termination voltage. Do not operate...

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