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Live at Power-Up

The Time it Takes an FPGA to Power Up has a Significant Impact on Effective System Design and the Total System Cost

Key Actel Benefits

— Level0, Best in Class, Live atPower-Up (LAPU) Support

Applications that require short initialization time cannot wait for deviceconfiguration upon power-up.

Actel Flash and antifuse FPGAs are the onlyFPGA device technology to support the best in class,Level0,live at power-up (LAPU) classification and are orders of magnitude faster to power-on than their nearest competitors.Unlike SRAM-based FPGAs,Actel devices do not require reloading when systempower is restored;glitches and brownouts in system power will not corrupt the Actel device configuration.As a result,there is no need for a configuration PROM,a power sequencing device,brownout detection,reset controller,and clock generator devices in the printed circuit board (PCB) design.Actel nonvolatile Level0 LAPU FPGAs speed initialization of system components and execute critical tasks up to 4,000 times sooner than SRAMor Hybrid FPGAs,and before the processor powers up and initializes.Criticaltasks include setup and configuration of memory blocks,clock generation, synthesis and distribution,and bus activity management.The live at power-up capability of Actel nonvolatile devices greatly simplifies total system design and reduces total system cost.Using live at power-up Actel FPGAs instead of SRAM or Hybrid FPGAs often eliminates the need for Complex Programmable Logic Devices (CPLDs),clock generation devices,and external PLLs.

— Operational Before Power-Up — Orders of Magnitude FasterPower-On than Competitors — Short System Initialization Time — Reduction of System Power-UpComponents — Effective and Robust SystemDesign — Reduced Total Cost ofOwnership