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FPGA, FPGA software, Integrated circuit, Gate array, Development kit
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| JHctel | |||||||||
| DSP Building Blocks RELIABILITY and PERFORMANCE with the SHORT DEVELOPMENT cycle of an fpga | |||||||||
| Actel offers a growing family of digital signal processing (DSP) cores for W'lll illiomrjlll si,;n;i| [iv.vi^il:*; .:l|v.iSi::l' ik,- lilh'riK!; illlll •III-11:1 ill t-onvu-sion. All of [hcsi' cores art: designed lor Acre! nonvohlilc Mash arid ,u:iiUl-c nielli tcctuic-. I kcv .lie flexible. 'i:th o|irnr.:/adi ins !o: perron nance 11]' si'/c.These omes have -.1 dislincl advance because [Ik:; .ire linn error immune .mil r-adljcloii-iolcr-anr icbcii used -airh Acrcl silicon. In addition, die live at [loucr-up fcuurc is ideal for miliuivv. commur.icaiion. aerospace, -and medical applications, where use!- need the extra rcli.iliilltv of no power-up delay. CoreFIR High Performance and Cost Effectiveness The Actel CoreFIR provides performance of up to 175 MHz, and will fit into devices as small as 30,000 gates (ProASIC'3) and 125,000 gates (Ajreelemtor"). CoreFIR can be configured to use a distributed arithmetic architecture thai is ;ui con unci Ik serialized :or -l/c-cthciciic procc-sins; and parallelized in- hii.ni pcrlorin-.iiii r applications, or ;i iniilliplicr. dqiciidinc: on inpin paramclcrs.The am- uses embedded RAM ill I en available 1» minimize si/c and maximize tdiniii^hpiic. | |||||||||
| • Distributed arithmetic (DA) algorithm • Multiple DA lookup table* to split for multiplier-free computation large number of taps | |||||||||