CoreSDR and CoreDDR Brochure - Actel - #1

Key Features

Synchronous Interface to External SDRAM

Support Standard SDRAM Chips and DIMMs up to 1,024 Mbytes of Memory

Pipelined Design Enables High Clock Rates with Minimal Routing Constraints

Bank Management Logic Monitors Status of Each SDRAM Bank with Up to 4 Banks Monitored

High-Performance Access Logic Allows Cascading of Read and Write Requests Enabling Up to 100% Throughput

Core Timing Parameters are Configurable at Run-Time

Run-Time Configurable Row, Column, and Bank Memory Settings

Support for Up to 8 Chips Selects

Automatic Generation of Initialization and Refresh Sequences

Available in Netlist and RTL Source Versions for Either Verilog or VHDL with a Comprehensive Testbench

The synchronous interface and fully pipelined internal architecture of SDRAM memories enables extremely fast data rates if used with an efficient SDRAM Controller. The Actel CoreSDR and CoreDDR SDRAM Controllers are intellectual property (IP) cores optimized for Actel FPGAs that provide a high performance, synchronous interface to standard SDRAM, for use in consumer, communication, industrial and military applications. With solutions for both SDR and DDR memory, Actel SDRAM controllers support up to 1,024 Mbytes of memory with a fully pipelined architecture that allows extremely fast data rates. Both CoreSDR and CoreDDR can be configured to provide a solution customized to your needs, based on system and memory-specific requirements. The SDRAM controllers offer full support for SDRAM bank and row manage­ment, support four-bank interleaving between commands, and execute all commands with maximum efficiency.

Actel FPGA Memory Controller System