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Actel’s ProASIC Family

The Only ASIC Design Flow FPGA

?ASIC-like Design Flow-Easy Timing Closure-Familiar Design Tools?Nonvolatile and Reprogrammable ?Low Power Consumption ?Flexible Embedded User Memory-Built in FIFO control logic?JTAG/IEEE 1149.1 Compliant ?High Performance Routing-100% Automatic Place and Routeat 100% utilization-Fix Pins at >90% utilization